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24AA02E48/24AA025E48
6.0
6.1
WRITE OPERATION
Byte Write
If the master should transmit more than 8 words (16 for
the 24AA025E48) prior to generating the Stop condi-
tion, the address counter will roll over and the previously
received data will be overwritten. As with the byte write
Following the Start condition from the master, the
device code (4 bits), the chip address (3 bits) and the
operation, once the Stop condition is received an inter-
nal write cycle will begin (Figure 6-2).
R/W bit which is a logic-low, is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will fol-
low once it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte transmit-
ted by the master is the word address and will be writ-
ten into the Address Pointer of the 24AAXXXE48. After
receiving another Acknowledge signal from the
24AAXXXE48, the master device will transmit the data
word to be written into the addressed memory location.
The 24AAXXXE48 acknowledges again and the mas-
ter generates a Stop condition. This initiates the inter-
nal write cycle and, during this time, the 24AAXXXE48
will not generate Acknowledge signals (Figure 6-1).
Note:
Page write operations are limited to writing
bytes within a single physical page
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’) and end at addresses that are
integer multiples of [page size – 1]. If a
page write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
6.2
Page Write
expected. It is therefore necessary for the
application software to prevent page write
The write-control byte, word address and the first data
byte are transmitted to the 24AAXXXE48 in the same
operations that would attempt to cross a
page boundary.
way as in a byte write. However, instead of generating
a Stop condition, the master transmits up to 8 data bytes
6.3
Write Protection
to the 24AAXXXE48, which are temporarily stored in the
on-chip page buffer and will be written into memory
once the master has transmitted a Stop condition. Upon
receipt of each word, the three lower-order Address
Pointer bits (four for the 24AA025E48) are internally
incremented by ‘ 1 ’. The higher-order five bits (four for
the 24AA025E48) of the word address remain constant.
The upper half of the array (80h-FFh) is permanently
write-protected. Write operations to this address range
are inhibited. Read operations are not affected.
The remaining half of the array (00h-7Fh) can be
written to and read from normally.
FIGURE 6-1:
BYTE WRITE
Bus Activity
Master
S
T
A
R
T
Control
Byte
Word
Address
Data
S
T
O
P
SDA Line
Bus Activity
S
1
0
1
0 A2* A1*A0* 0
Chip
Select
Bits
A
C
K
A
C
K
A
C
K
P
Note:
* Bits A0, A1 and A2 are “don’t cares” for the 24AA02E48.
FIGURE 6-2:
PAGE WRITE
Bus Activity
Master
S
T
A
R
T
Control
Byte
Word
Address (n)
Data (n)
Data (n + 1)
Data (n + 7)
S
T
O
P
S 1 0 1 0 A2 A1 A0 0
SDA Line
* * *
P
Bus Activity
Chip
Select
Bits
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Note:
* Bits A0, A1 and A2 are “don’t cares” for the 24AA02E48.
? 2010 Microchip Technology Inc.
DS22124D-page 9
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